[From the last episode: We looked at the critical role that clocks play in digital circuits.]
We’ve seen that clocks help to keep order in digital logic. You’d think that, as a matter of course, you’d want to run them as fast as possible for the fastest speed. Even if they’re not doing anything at the moment, what harm could a clock just ticking away do?
Historically, it would do no harm. But that was before we cared about powerThe rate of energy consumption. For electricity, it’s measured in watts (W). as much as we do now. We’ve looked at how power is strongly related to voltageVoltage is what gets electrons to flow. It's analogous to water pressure, which gets water to flow. Voltage is measured in units of "volts.", but that’s not all that affects power. Clock frequencyThe rate of change of a signal, specified in hertz, or cycles per second. does too.
Faster Means Higher Power
Without going into too much detail, we can put down a quick relationship between clock or signal frequency (f) and power (P):
The k here is just some constant; we won’t worry about what it is. What the rest of it says is that power increases with the square of voltage (V, which we already saw) and with frequency as well. The dependency on frequency isn’t as strong as the dependency on voltage, of course. If voltage doubles, then power quadruples. If frequency doubles, then power “only” doubles as well.
So, unlike the old days, where you might be able to run things as fast as possible, we’ve been rethinking that for some years now. There are really two big outcomes from this dependency:
- We should run clocks only as fast as we really need.
- If nothing is happening, we should shut the clock down.
The first of those is the most obvious one, but it’s not a guarantee of lower energy, as we’ll see next week. It depends on what “how fast we need” really means.
The second of those is being used a lot these days. You may remember that a clock domain is a chunk of the circuitry that’s controlled by a single clock. It’s very much similar in concept to a voltage domain, which we already looked at.
Shutting Down the Clocks
And, just as we could save power by shutting down the voltage on domains that we aren’t using, we can also save power by shutting down the clocks in domains that we aren’t using. That means putting a gate in the clock path. That gate can block the clock signal from getting to its destinations. The more granular control you want, the more you chop the circuit up into different domains controlled by different gates.
All you need, then, is the logic that decides when to turn on which gates. That might even be controlled by systemThis is a very generic term for any collection of components that, all together, can do something. Systems can be built from subsystems. Examples are your cell phone; your computer; the radio in your car; anything that seems like a "whole." softwareIn this context, "software" refers to functions in an IoT device that are implemented by running instructions through some kind of processor. It's distinct from "hardware," where functions are built into a silicon chip or some other component..
But there is one consideration that is always important when playing with clocks – especially when you have different domains with different clocks and signals that may transition from one domain to another. It also applies to the clock gating signals.
A Special Kind of Instability
To understand this better, picture yourself driving down the road towards a stoplight that’s green. If it turns red soon enough, you’ll stop with no problem. If it turns red while you’re just about to enter, you’ll go through legally and it’s no problem. But there’s that small window of time where, if it turns red, you’re not sure: do I hit the brake or the accelerator? You might actually go back and forth: Brake! No, accelerator! No, brake!
A similar confusion can happen with clocks. It’s called metastability. When a clock gets to a register, a signal needs to be there enough ahead of time, and it usually has to stick around for a little time after the clock (so-called setup time and hold time). Do that right, and you’re good.
But if the clock or signals are slightly delayed such that the clock arrives in that tiny window of time where it’s not sure, “Wait, is there a stable signal ready to go or not?”, then the register can literally go haywire, with an oscillating output. Instead of, “Brake! No, accelerator!”, it’s “High! No, low! No, high!” And it takes a while to ring down and stabilize.
As you can imagine, this can really screw things up. So it has to be avoided. Designers have to take this into account when signals go from one clock domain, where they might have been well aligned with that clock, into another domain, where the different clock might have different timing. In addition, when adding delays to the clock in the way that a clock gate would, they have to take that delay into account to be sure that all the signals will be stable with the right timing.
As usual, there’s no such thing as an easy fix here. There are solutions, but they require work to make sure that all the circuitry can still hum along like a well-oiled machine.
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